Electronic component package fabrication method
US8664090B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2012 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | May 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a first buildup dielectric layer on a wafer. The wafer includes electronic components delineated from one another by singulation streets. A singulation street exposure light trap layer is formed on the singulation streets. A second buildup dielectric layer is applied and patterned by being selectively exposed to an exposure light. The singulation street exposure light trap layer traps and diffuses the exposure light thus preventing the exposure light from being reflected to the portion of the second buildup dielectric layer above the singulation streets. In this manner, complete removal of the second buildup dielectric layer above the singulation streets is insured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.