Dual sidewall spacer for seam protection of a patterned structure

US8664102B2 · kind B2 · utility

Assignees

• TOKYO ELECTRON LIMITED · JP
• International Business Machines Corporation · US

Inventors

• David L. O'Meara · Albany, US
• Anthony Dip · Mabank, US
• Aelan Mosden · Poughkeepsie, US
• Pao-Hwa Chou · Nirasaki, JP
• Richard A. Conti · Altamont, US

Key dates

• Filing date: Mar 31, 2010
• Grant date: Mar 4, 2014
• Expiry date: Nov 1, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.