Method of patterning a semiconductor device with hard mask
US8664111B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Sep 30, 2011 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Feb 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.