Condensed memory cell structure using a FinFET

US8665629B2 · kind B2 · utility

Assignees

• Qimonda AG · DE
• Altis Semiconductor, SNC · FR

Inventors

• Human Park · Paris, FR
• Ulrich Klostermann · Fontainebleau, FR
• Rainer Leuschner · Regensburg, DE

Key dates

• Filing date: Sep 28, 2007
• Grant date: Mar 4, 2014
• Expiry date: Dec 13, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.