Memory circuit and control method thereof
US8665663B2 · kind B2 · utility
6Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2011 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | May 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit according to one embodiment of the present invention includes a clock driver and an ODT timer. The clock driver is configured to provide a system clock signal based on a root clock signal when the memory circuit is in a read mode, and is configured to stop providing the system clock signal when the memory circuit is not in the read mode. The ODT timer is configured to provide a system ODT signal when the memory circuit is not in the read mode, wherein the transition edge of the system ODT signal is aligned with the transition edge of the root clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.