Pipelined packet switching and queuing architecture
US8665875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2011 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Sep 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/602
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network is disclosed. The linecard has two paths: a receive path and a transmit path. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information. Each packet is buffered and enqueued for transmission over the switching fabric to a destination linecard. The transmit path includes a buffer/queuing circuit similar to that used in the receive path. Both enqueuing and dequeuing of packets is accomplished using a CoS-based decision making apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.