Heterogeneous multi-core integrated circuit and method for debugging same
US8666690B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2011 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Oct 29, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3656
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A heterogeneous multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. A debug control circuit is connected between the first and second TAP controllers and the first and second debug ports. Based on external configuration signals, the debug control circuit configures the connections between the first and second TAP controllers and the first and second debug ports according to predetermined configuration modes, which allows flexibility in debugging the heterogeneous multi-core integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.