Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost
US8667439B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2013 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Aug 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of various hosts in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example implementations selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, and using probabilistic functions to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.