Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices

US8669167B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Josephine B. Chang · Mahopac, US
• Isaac Lauer · Yorktown Heights, US
• Chung-Hsun Lin · White Plains, US
• Jeffrey W. Sleight · Ridgefield, US

Key dates

• Filing date: Aug 28, 2012
• Grant date: Mar 11, 2014
• Expiry date: Aug 28, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/011

Abstract

Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided.