Viewing and debugging HDL designs having SystemVerilog interface constructs
US8671383B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 10, 2012 |
| Grant date | Mar 11, 2014 |
| Priority date | — |
| Expiry date | Apr 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for viewing and debugging HDL designs having SystemVerilog interface constructs are provided. An HDL design code is received, wherein the design code comprises a first module, a second module and a SystemVerilog interface construct. A first object corresponding to the first module, a second object corresponding to the second module and an interface object corresponding to the interface construct are displayed in a schematic view. The interface object is disposed between the first and second objects, and a shape of the interface object is different from that of the first and second objects. The interface signals from the first object to the second object and the interface signals from the second object to the first object pass through the interface object.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.