Sidewall image transfer process with multiple critical dimensions
US8673165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2011 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Apr 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0337
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.