Multilayer sidewall spacer for seam protection of a patterned structure
US8673725B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 31, 2010 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Feb 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.