Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices

US8673731B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Josephine B. Chang · Mahopac, US
• Isaac Lauer · Yorktown Heights, US
• Chung-Hsun Lin · White Plains, US
• Jeffrey W. Sleight · Ridgefield, US

Key dates

• Filing date: Aug 20, 2012
• Grant date: Mar 18, 2014
• Expiry date: Aug 20, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.