Methods to reduce gate contact resistance for AC reff reduction
US8674457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2010 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Nov 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.