Microelectronic package and method of manufacturing same
US8674519B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2010 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Aug 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package includes a substrate (110, 210), an interposer (120, 220) having a first surface (121) and an opposing second surface (122), a microelectronic die (130, 230) attached to the substrate, and a mold compound (140) over the substrate. The interposer is electrically connected to the substrate using a wirebond (150). The first surface of the interposer is physically connected to the substrate with an adhesive (160), and the second surface has an electrically conductive contact (126) formed therein. The mold compound completely encapsulates the wirebond and partially encapsulates the interposer such that the electrically conductive contact in the second surface of the interposer remains uncovered by the mold compound.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.