Field programmable gate array utilizing two-terminal non-volatile memory
US8674724B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2011 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Jul 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.