Method to reduce program disturbs in non-volatile memory cells
US8675405B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2013 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Jun 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.