Recessing and capping of gate structures with varying metal compositions
US8679909B2 · kind B2 · utility
10Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2012 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Jun 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.