Methods for fabricating semiconductor devices with isolation regions having uniform stepheights

US8679940B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Frank Jakubowski · Dresden, DE
• Jorg Radecker · Dresden, DE
• Frank Ludwig · Dresden, DE

Key dates

• Filing date: Feb 17, 2012
• Grant date: Mar 25, 2014
• Expiry date: May 25, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/117
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming a planarization stop layer overlying a semiconductor substrate. A trench is etched through the planarization stop layer and into the semiconductor substrate and is filled with an isolation material. The isolation material is planarized to establish a top surface of the isolation material coplanar with the planarization stop layer. In the method, a dry deglaze process is performed to remove a portion of the planarization stop layer and a portion of the isolation material to lower the top surface of the isolation material to a desired stepheight above the semiconductor substrate.