Semiconductor package substrates having layered circuit segments, and related methods
US8686568B2 · kind B2 · utility
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66References
19Claims
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Key dates
| Filing date | Sep 27, 2012 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Sep 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.