Bonding layer structure and method for wafer to wafer bonding
US8686571B2 · kind B2 · utility
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5References
14Claims
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Key dates
| Filing date | Aug 9, 2012 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Aug 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15788
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure comprises a first semiconductor substrate, a first bonding layer deposited on a bonding side the first semiconductor substrate, a second semiconductor substrate stacked on top of the first semiconductor substrate and a second bonding layer deposited on a bonding side of the second semiconductor substrate, wherein the first bonding layer is of a horizontal length greater than a horizontal length of the second semiconductor substrate, and wherein there is a gap between an edge of the second bonding layer and a corresponding edge of the second semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.