Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor

US8691644B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Seung-Chul Song · Plano, US
• Amitabh Jain · Allen, US
• Deborah J. Riley · Sachse, US

Key dates

• Filing date: Jul 5, 2012
• Grant date: Apr 8, 2014
• Expiry date: Jul 5, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0181

Abstract

A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.