Methods of manufacturing semiconductor device
US8691693B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2011 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Nov 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.