Methods, apparatuses, and circuits for bimodal disable circuits
US8692603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2013 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Aug 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.