Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features
US8693236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2012 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Feb 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line in hierarchy, and associated systems and methods are described. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line, and wherein the sectioned bit lines are arranged in hierarchical arrays. In other implementations, a hierarchical SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.