Patent · US Active

Wear leveling for erasable memories

US8694718B2 · kind B2 · utility

2Cited by

2References

14Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

Massimo Iaculo · San Marco Evangelista, IT
Ornella Vitale · Cicciano, IT
Antonino Pollio · Vico Equense, IT

Key dates

Filing date	Dec 30, 2008
Grant date	Apr 8, 2014
Priority date	—
Expiry date	Mar 22, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/7211
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In accordance with some embodiments, wear leveling may be done based on the difference in age of discarded blocks and engaged blocks. Data is moved to an older discarded block from a younger engaged block. Two wear leveling bits may be used for each logical block, such that the wear leveling bits are used in alternating cycles.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.