Method of forming an asymmetric poly gate for optimum termination design in trench power MOSFETS
US8697520B2 · kind B2 · utility
2Cited by
10References
21Claims
0Family size
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Key dates
| Filing date | Mar 2, 2012 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Aug 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.