Memory buffering system that improves read/write performance and provides low latency for mobile systems
US8700830B2 · kind B2 · utility
3Cited by
7References
19Claims
0Family size
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Key dates
| Filing date | Nov 20, 2007 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | May 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.