Nonvolatile memory with write cache having flush/eviction methods
US8700840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2009 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Oct 6, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.