Integrated circuit packaging system with warpage preventing mechanism and method of manufacture thereof
US8703535B2 · kind B2 · utility
4Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2012 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Jun 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate; connecting an integrated circuit die to the package substrate with an internal interconnect; and forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.