Packaged semiconductor chips
US8704347B2 · kind B2 · utility
0Cited by
73References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2010 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Aug 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and a ball grid array formed over a surface of the packaging layer and being electrically connected to the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.