Stacked die assembly
US8704384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2012 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Mar 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked die assembly for an IC includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first integrated circuit die and the second integrated circuit die via the first integrated circuit die avoiding the interconnect restricted area of the first interposer and the second interposer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.