Patent · US Active

Erase techniques and circuits therefor for non-volatile memory devices

US8705283B2 · kind B2 · utility

2Cited by

4References

18Claims

0Family size

Inventors

Vincenzo Ferragina · Pavia, IT
Stefano Surico · Milano, IT
Giuseppe Moioli · Albino, IT
Simone Bartoli · Pessano, IT

Key dates

Filing date	Jul 13, 2011
Grant date	Apr 22, 2014
Priority date	—
Expiry date	May 22, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/0483
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.