Patent · US Active

Access methods and circuits for memory devices having multiple banks

US8705310B2 · kind B2 · utility

4Cited by

14References

20Claims

0Family size

Assignee

Cypress Semiconductor Corporation · US

Inventors

Thinh Tran · Palo Alto, US
Joseph Tzou · Belmont, US
Jun Li · Palo Alto, US

Key dates

Filing date	Dec 26, 2012
Grant date	Apr 22, 2014
Priority date	—
Expiry date	Dec 26, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/419
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method can include storing bank addresses, if received, on at least rising and falling edges of a same clock cycle; and if addresses stored on the rising and falling edges of the same clock cycle correspond to different banks of a memory device, starting accesses to both banks after the falling edge of the clock cycle; wherein any of the banks can be accessed in response to an address stored on a rising edge of a next clock cycle. Devices and additional methods are also disclosed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.