Fault tolerant stability critical execution checking using redundant execution pipelines
US8707094B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2013 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Mar 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/845
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.