Integrated circuit packaging system with interconnects and method of manufacture thereof
US8709932B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2010 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Feb 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a contact pad; forming a first resist layer, having a first resist opening, over the carrier and the contact pad, the first resist opening partially exposing the first contact pad; forming a second resist layer, having a second resist opening over the first resist opening, the second resist opening partially exposing the first resist layer; mounting an integrated circuit over the carrier; and forming an internal interconnect between the integrated circuit and the carrier, the internal interconnect filling the second resist opening with no space between the second resist layer in the second resist opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.