Lead frame array package with flip chip die attach
US8710636B1 · kind B1 · utility
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4References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 4, 2013 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Feb 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A small form factor near chip scale package is provided that includes input/output contacts not only along the periphery of the package, but also along the package bottom area. Embodiments provide these additional contacts through use of an array lead frame coupled to under die signal contacts through the use of flip chip bonding techniques. The array lead frame contacts are electrically isolated through the use of a partial sawing process performed during package singulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.