Redistribution layer (RDL) with variable offset bumps
US8710656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2012 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Jul 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL layer, the BEOL layer having a plurality of bond pads, each bond pad connected to at least one corresponding metal via through the RDL; and a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip. In one embodiment, the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding solder bump pad structure for that solder bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.