Bit error mitigation
US8713409B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2012 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Nov 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches for mitigating single event upsets (SEUs) in a circuit arrangement. In response to each bit error of a plurality of bit errors, an error address indicative of the bit error in a configuration memory cell in the circuit arrangement is translated into a non-volatile memory address. A partial bitstream at the non-volatile memory address is read from a non-volatile memory. Successive partial bitstreams read in response to successive ones of the bit errors are alternately transmitted to first and second internal configuration ports. A subset of configuration memory cells of the circuit arrangement, including the configuration memory cell referenced by the error address, is reconfigured with the partial bitstream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.