Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain
US8716091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2010 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Dec 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an upside-down p-FET includes: fully etching source and drain regions in a donor substrate by etching a silicon-on-insulator layer through buried oxide and partially etching the silicon substrate; refilling a bottom and sidewall surfaces of the etched source and drain regions with epitaxial silicide/germanide to form e-SiGe source and drain regions; capping the source and drain regions with self-aligning silicide/germanide; providing a silicide layer formed over the gate conductor line; providing a first stress liner over the gate and the e-SiGe source and drain regions; depositing a planarized dielectric over the self-aligning silicide/germanide; inverting the donor substrate; bonding the donor substrate to a host wafer; and selectively exposing the buried oxide and the e-SiGe source and drain regions by removing the donor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.