Three-dimensional memory array stacking structure
US8716780B2 · kind B2 · utility
22Cited by
12References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2010 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Aug 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a planar substrate, a plurality of horizontal conductive planes above the planar substrate, and a plurality of horizontal insulating layers interleaved with the plurality of horizontal conductive planes. An array of vertical conductive columns, perpendicular to the pluralities of conductive planes and insulating layers, passes through apertures in the pluralities of conductive planes and insulating layers. The memory device includes a plurality of programmable memory elements, each of which couples one of the horizontal conductive planes to a respective vertical conductive column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.