System and method for soft error detection in memory devices
US8717829B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2012 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Jan 2, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for detecting soft errors in a memory device includes a latch, a master flip-flop and a slave flip-flop. The latch receives input data (control and/or address signals) at the beginning of a memory operation in response to a rising edge of a first clock signal. The output of the latch is provided to the master flip-flop. The master flip-flop continuously receives and stores the latch output during the memory operation based on a second clock signal. The slave flip-flop receives and stores the output of the master flip-flop at the end of the memory operation based on the second clock signal. A comparator compares the input data with the output of the slave flip-flop to detect soft errors that occur during the memory operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.