Method for forming a via contacting several levels of semiconductor layers
US8722471B2 · kind B2 · utility
1Cited by
2References
8Claims
0Family size
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Key dates
| Filing date | Jan 23, 2013 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Jan 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.