Interfacial layer for DRAM capacitor
US8722504B2 · kind B2 · utility
5Cited by
1References
20Claims
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Key dates
| Filing date | Sep 21, 2011 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Oct 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
A method for reducing leakage current in DRAM capacitor stacks by introducing dielectric interface layers between the electrodes and the bulk dielectric material. The dielectric interface layers are typically amorphous dielectric materials with a k value between about 10 and about 30 and are less than about 1.5 nm in thickness. Advantageously, the thickness of each of the dielectric interface layers is less than 1.0 nm. In some cases, only a single dielectric interface layer is used between the bulk dielectric material and the second electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.