Voids in STI regions for forming bulk FinFETs
US8723271B2 · kind B2 · utility
10Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2013 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Jun 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.