Architecture for a 3D memory array
US8724390B2 · kind B2 · utility
18Cited by
4References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2011 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Apr 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.