Testing of SRAMS
US8726114B1 · kind B1 · utility
3Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2012 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Dec 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and other embodiments associated with at-speed testing of static random access memory (SRAM) are described. In one embodiment, a method includes loading, into a multi-stage pipeline of memory devices, a control pattern for testing a static random access memory (SRAM). The SRAM is tested by generating a test input that is based, at least in part, on the control pattern from the multi-stage pipeline of flip-flops. The test input is provided to the SRAM over a series of clock cycles that are at a core clock speed of the SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.