Patent · US Active

Gate electrodes of a semiconductor device formed by a hard mask and double exposure in combination with a shrink spacer

US8728924B2 · kind B2 · utility

0Cited by

1References

9Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Sven Beyer · Dresden, DE
Andreas Hellmich · Dresden, DE
Steffen Laufer · Dresden, DE
Klaus Gebauer · Krefeld, DE

Key dates

Filing date	Jul 21, 2011
Grant date	May 20, 2014
Priority date	—
Expiry date	Jul 21, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/601
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

When forming complex gate electrode structures, a double exposure double etch strategy may be applied, in which the lateral distance in the width direction of the gate electrode structures may be defined prior to forming mask features for defining the gate length. In this case, the width dimension of the mask opening may be adjusted on the basis of a spacer element, which may thus allow providing a reduced dimension on the basis of well-established process techniques.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.