Circuits and methods for placing programmable impedance memory elements in high impedance states
US8730752B1 · kind B1 · utility
7Cited by
28References
23Claims
0Family size
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Key dates
| Filing date | Apr 2, 2012 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Jun 20, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0073
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include a load circuit coupled in series with at least one memory element between two nodes and configured to enable a programming current to flow through the memory element to lower its impedance, and configured to enable an erase current to flow through the element in a direction opposite to the program current, the erase current varying in response to an erase voltage applied across the two nodes as the memory element impedance increases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.