Memory apparatus and system with shared wordline decoder
US8730754B2 · kind B2 · utility
2Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2011 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Mar 8, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.